A bipolar-CMOS-DMOS (BCD) process is a system-on-chip (SOC) technique used generally in automotive applications, a printer head driver, a monitor control, etc. An LDMOS can be used as a main device in the BCD process, and can be used mainly in a power integrated circuit (PIC). An LDMOS device can have a high input impedance compared with a bipolar transistor, and thus, can have a large power gain and a simple gate driving circuit. Furthermore, since the LDMOS device is a unipolar device, there is no time delay caused by storage or recombination of minority carriers while the device is turned off.
As illustrated in example FIG. 1, provided is a push-pull or bridge structure having LDMOS devices m1 and m2 which drives inductor loads. Diodes indicate body diodes of the LDMOS devices. LDMOS devices m1 and m2 drive the inductor loads through current routes Im1 and Im2. Hereinafter, LDMOS m1 is referred to as a high side LDMOS, and LDMOS m2 is referred to as a low side LDMOS.
As illustrated in example FIG. 2, a general high side LDMOS is provided including P-type semiconductor substrate 202 having N-type buried layer 204 formed thereon and/or thereover, and a P-type epitaxial layer. N-type buried layer 204 can serve to reduce the width of a depletion layer extended from P-type body 210, and thus, to substantially raise a punch-through voltage when a voltage is applied to N+-type drain area 218. Further, the P-type epitaxial layer, when semiconductor crystals in a gas state are extracted on a single crystal wafer serving as a substrate, serves to allow the crystals to be grown along the crystal axis of P-type substrate 202 and to reduce the resistance of P-type substrate 202. Thereafter, N-type deep well 206 is formed on and/or over P-type semiconductor substrate 202 and deep well cutout area 208 is formed by coating P-type semiconductor substrate 202 with a mask when ion implantation for forming N-type deep well 206 is performed. P-type body 210 is formed in N-type deep well 206. A channel area is formed around the surface of P-type body 210 between a contact surface between P-type body 210 and N-type deep well 206 and N+-type source area 220 by applying a bias voltage to gate area 214. Deep well cutout area 208 is formed by coating P-type semiconductor substrate 202 with a mask when ion implantation for forming N-type deep well 206 is performed, and thus, serves to raise a breakdown voltage when a high voltage is applied to N+-type drain area 218 on condition that the high side LDMOS is turned on. Thereafter, insulating layer 212 is formed at an active area and a field area and includes a field oxide film, such as silicon oxide film, which is thermally grown. Thereafter, gate area 214 is formed and shallow N-type well 216, N+-type source area 220, N+-type drain area 218 and P+-type impurity layer 222 for enhancing a contact with P-type body 210 are formed.
The high side LDMOS device limits an operation voltage so as to avoid the generation of breakdown when the device is turned on. When the operation voltage is raised, the electric field of a gate edge is raised, a body current is increased, and the capacity of a long term safe operating area (SOA) is degraded. Accordingly, it is difficult to implement an LDMOS having a higher operating voltage in a BCD process. In order to raise the breakdown voltage, a method can be used in which the thickness of the P-type epitaxial layer is increased and the width of deep well cutout area 208 is widened. However, this method also results in an increase in the on-resistance (Rsp) of the LDMOS device, and thus, is not proper for the increase in the overall usefulness of the LDMOS device.